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AR# 63913

Zynq - Marginal SDIO timing on ZC702 and ZC706 can lead to data CRC error while initiating write to SD device

Description

Xilinx ZC702 and ZC706 boards do not compensate for channel skew in the Maxim MAX13035E level translator resulting in possible violation of the 2.0ns input hold time as defined in the SDIO specification. 

This can lead to a CRC error during write to an SD card that requires the maximum hold time.

This issue has been observed only with Swissbit SD cards. 

On some ZC702 and ZC706 boards, the data hold time measured near J30 (SD connector) has been observed to be 1.8 ns which is marginal to the value mentioned in the SDIO specification and might cause data CRC errors while attempting to write to SD device.

Solution

To resolve this issue, do the following:

  • On custom boards with a level shifter, the SD_DAT[0:3] and SD_CMD lines must be lengthened to compensate for the maximum channel skew as specified in the level shifter data sheet.
    This will guarantee SDIO hold time requirements are met at the SD card.
     
  • On ZC702 and ZC706 boards, use an SD card from a vendor which does not require the maximum input hold time.
    No issues have been observed with the SD card that is shipped with the kit.
AR# 63913
Date Created 03/13/2015
Last Updated 04/09/2015
Status Active
Type General Article
Devices
  • Zynq-7000
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit
  • Zynq-7000 All Programmable SoC ZC706 Evaluation Kit