UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63949

2014.4 Vivado SysGen - CORDIC output data is always zero if cartesian_tvalid is not always 1

Description

If "cartesian_tvalid" is not always 1, both "dout_tdata_imag" and "dout_tdata_real" are always zero.

The "tvalid" behaves correctly.

What can cause this problem?

Solution

This issue only occurs on CORDIC v6.0.


CORDIC v5.0 did not have this problem and behaved correctly.

The available work-around is to expose "aresetn" and "aclken" and then connect both of them to boolean 1.

A fix is expected in a future revision of the tools.

AR# 63949
Date Created 03/18/2015
Last Updated 05/22/2015
Status Active
Type General Article
Tools
  • System Generator for DSP
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
IP
  • CORDIC