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AR# 63950: 7 Series Config - I/Os may appear to have a weak pull-up enabled between the assertion of PROG_B, and when PUDC is sampled on the falling edge of INIT_B. Can I keep the value of PUDC during this period?
7 Series Config - I/Os may appear to have a weak pull-up enabled between the assertion of PROG_B, and when PUDC is sampled on the falling edge of INIT_B. Can I keep the value of PUDC during this period?
In 7 series devices, PUDC dictates the state of the I/Os during configuration.
Regardless of the value of PUDC, if PROG_B is asserted on a configured device, a pull-up may appear on the line of all I/O until just after PUDC is sampled on the falling edge of INIT_B (~100ns).
Why is there a pull-up present during reconfiguration?
Can I turn it off?
On a configured device, PUDC is sampled on the falling edge of INIT_B.
The use of PUDC in the user design determines if a PULLUP on all I/O is present prior to INIT_B assertion.
If the PUDC pin is used in the current design - The presence of a weak PULLUP on all I/O will be dictated by the level seen on the PUDC pin. (Logic HIGH - NO PULLUP, Logic LOW - PULLUP)
If the PUDC pin is not used in the current design (i.e. it is an unused pin) - The weak PULLUP will always be enabled between PROG_B assertion and just after INIT_B asserts.
If the state of the I/O is relevant on a design that is being reconfigured, using the PUDC pin as an input can ensure that the value seen on PUDC dictates the presence of a pull-up between the assertion of PROG_B and INIT_B.
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