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AR# 63952

2015.x Vivado - IP Flows Known Issues

Description

This answer record contains known issues for Vivado Design Suite 2015.x related to IP core flows, including IP customization, IP generation, IP Packager, IP Catalog and integration of IP cores in the Vivado design environment.

Solution

Outstanding Known IP Flow Issues in Vivado 2015.4

(Xilinx Answer 60195) Editing a packaged IP in IP Packager and then discarding those edits might not completely remove all HDL file edits
(Xilinx Answer 64051) UltraScale MIG ELF file is not correctly populated when using Non-project mode
(Xilinx Answer 66114) ERROR: [BD 41-237] Bus Interface property DATA_WIDTH does not match between /axi_mem_intercon/m01_couplers/auto_pc/S_AXI(32) and /axi_mem_intercon/m01_couplers/auto_cc/M_AXI(512)
(Xilinx Answer 66285) XSDB give message:Cannot stop MicroBlaze. Stalled on instruction fetch
(Xilinx Answer 66286) DisplayPort TX Subsystem IP errors in Generating Outputs : ERROR: [BD 41-1273] Error running post_propagate TCL procedure: invalid command name "::bd::addr::get_addresses_of" in managed IP project
(Xilinx Answer 66291) AXI 10g Ethernet Example Design created from IPI AXI 10g Ethernet block fails in OOC generation with ERROR: [Synth 8-439] module 'bd_0_ten_gig_eth_pcs_pma_0' not found
(Xilinx Answer 66292) Sub-core reference is not updated for migrated project even though the parent IP core was upgraded
(Xilinx Answer 66395) Creating an example design for the GT Wizard IP instance gives: [Common 17-69] Command failed: ERROR:HACGExampleFork: Invalid script name specified
(Xilinx Answer 66403) Video Processing Subsystem IP core in a Block Design does not fully generate the first time
(Xilinx Answer 66407) Generating Output products (OOC per IP) on a hierarchical IP fails with [exportsim-Tcl-66] failed to open file to write (export_sim_options.cfg)


Known IP Flow Issues Resolved in Vivado 2015.4

(Xilinx Answer 66281) Exported simulation script fails for AXI bridge for PCIe Express and PCIe DMA subsystem

Known IP Flow Issues Resolved in Vivado 2015.3

(Xilinx Answer 63930) Show hierarchy button is grayed out if the .xci file is under the hierarchy of another .xci file
(Xilinx Answer 64107) When using the direct instantiation method the synthesis fails, error in non-project mode without module declaration
(Xilinx Answer 64277) A user defined interface for a packaged IP is not recognized in a new IPI project
(Xilinx Answer 64385) After removing an IP from my Block Design which I have packaged into a Custom IP, the IP Package XML file still references the IPs XCI file
(Xilinx Answer 64673) Using a custom IP containing a MIG core can produce an error where the PRJ file cannot be read when trying to generate the custom IP
(Xilinx Answer 64874) Synthesis fail after making changes within the Block Design (BD)
(Xilinx Answer 65498) 2015.2 Vivado - IP Status Report shows the IP Status of the AXI Interconnect as "Newer Version Available. IP Revision Change," but unable to upgrade
(Xilinx Answer 65516) Generating targets for OOC block Design in projectless flow gives [Common 17-53] User Exception: No open project
(Xilinx Answer 65559) Export Hardware with pop-up: Export hardware - BD needs generation of the output products for the export hardware

Known IP Flow Issues Resolved in Vivado 2015.2

(Xilinx Answer 64149) UltraScale GT is not creating the clocks rxoutclk or txoutclk in the IP core's OOC run
(Xilinx Answer 64229) IP Packager does not imported parameters if they are marked as hidden
(Xilinx Answer 64276) I get a java.lan.nullPointerException when selecting context menu option "Associate Clocks..." in Ports and Interfaces workspace from IP Packager
(Xilinx Answer 64383) IP File Groups in Packaged user IP are not automatically updated when a new IP from the IP Catalog is added to a project


Known IP Flow Issues Resolved in Vivado 2015.1

(Xilinx Answer 60477) Create peripheral in IP Packager gives Internal Exception error when creating AXI4 peripheral if default vendor is blank
(Xilinx Answer 63065) Generating IP using Tcl commands creates '_funcsim.vhdl/.v' files in incorrect language
(Xilinx Answer 63111) Vivado will generate IP core stub file in root directory when project is on a mapped drive
(Xilinx Answer 63250) The IP catalog might flicker and hang if a project is pointing to an invalid IP repository
(Xilinx Answer 63865) Interface IP ports list is missing from custom packaged IP
(Xilinx Answer 63916) When creating a custom interface, the "Max Slaves" entry disappears if it is saved with a value of '0'

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
63538 Vivado Design Suite 2015 - Known Issues N/A N/A
AR# 63952
Date Created 03/18/2015
Last Updated 04/18/2016
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.4