We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63963

Vivado 2014.4.1- Carry8 Pin-mapping Issue in Vivado Tool for UltraScale Design may lead to design failure


There is a restriction in UltraScale devices that the DI[0] and CI pins of Carry8 cells cannot be driven by the same net.

Vivado revisions prior to 2015.1 do not observe this restriction, so it is possible for UltraScale designs to pass the post route simulation, but fail in hardware with a functional problem related to the output(s) of a carry8 in the design. 


This problem has been fixed for Vivado 2015.1.

The router is fixed to map the DI[0] pin to a LUT route-thru instead of AX, when AX is used for CI.

This fix should affect situations where CI and DI[0] are driven by the same net.
AR# 63963
Date 04/30/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
Page Bookmarked