You can perform functional simulation after synthesis or implementation.
It allows you to ensure that the synthesized or implemented design meets the functional requirements and behaves as expected.
This article describes the two ways to run functional simulation using Vivado Simulator: from the Vivado IDE and from the command line.
1) Generate a functional simulation netlist.
The functional simulation netlist is a hierarchical, folded netlist that is expanded to the primitive module or entity level. The lowest level of hierarchy consists of primitives.
The following Tcl commands take a synthesized or implemented design database and write out a single netlist for the entire design.
Warning: Running the write_verilog command in a Synthesis post.tcl script will not work properly if the design contains IP modules with output products generated as out of context (OOC) modules.
The synthesis process will not have access to these OOC modules and will see them as black boxes. The correct option in this case would be to open the synthesized design (loads the design from the project level) and then run write_verilog.
2) In many cases, you can use the same test bench that you used for behavioral simulation to perform a more accurate simulation.
As in behavioral simulation, either parse the individual files or a project file, elaborate and generate a snapshot, and then simulate.
For more information on using Vivado Simulator and the command line options, please refer to (UG900) Vivado Design Suite User Guide: Logic Simulation.