The majority of Xilinx IP have their synthesizable sources and behavioral simulation models in a single language (VHDL or Verilog).
This effectively disables simulation for language-locked simulators if you are not licensed for the appropriate language.
The Target Language setting is used to:
- Deliver IP output product in the desired language if both languages are available.
If only one language is available, the Target Language setting is ignored and the sources are delivered in the available HDL language.
- Deliver instantiation templates in the desired language.
- Deliver the IP behavioral simulation model in the desired language if available.
- Deliver a structural simulation model which is automatically generated from the IP's DCP When the IP behavioral simulation model in the desired language is unavailable.
Note: The simulator_language property cannot deliver a language-specific simulation netlist file if the generated Synthesized checkpoint (.dcp) is disabled.
When the IP supports both languages and either language could be used for simulation, set the simulator_language property to Mixed and use the target_language property to deliver simulation models.
Vivado Simulator is a mixed language simulator and can handle simulation models in both VHDL and Verilog.
If you are using other simulators and have a license for a single language only, change the simulator language to match your license.
If the IP does not deliver a behavioral model or does not match the chosen and licensed simulator language, the Vivado tools automatically generate a structural simulation model (_funcsim.v or _funcsim.vhdl) to enable simulation.
For more details on how the simulator_language property controls the delivery of the IP simulation model, please refer to (UG900) Vivado Design Suite User Guide: Logic Simulation, under the section "Understanding the Simulator Language Option".