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AR# 63997

2014.4 UltraScale Hierarchical Design - False DRC (RTSTAT-2) is reported that out_of_context clock is unrouted or partially routed


In an out_of_context (OOC) design targeting on UltraScale device, the following DRC is reported for the clock signal:

ERROR: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem bus(es) and/or net(s) are XX_clk.

Is this DRC correct?


DRC should not report OOC clocks as unrouted or partially routed in UltraScale. 

In Vivado 2015.1, this DRC will be removed for these circumstances.

You can work around this issue in Vivado versions prior to 2015.1 by reducing the severity of the RTSTAT-2 check: 

set_property severity warning [get_drc_checks RTSTAT-2] 
AR# 63997
Date 04/02/2015
Status Archive
Type General Article
  • Vivado Design Suite - 2014.4
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