This connection is now illegal.
From Vivado 2015.1, DRC HDPR59 is added to avoid this type of topological structure:
Rule violation (HDPR-59) Illegal clock load '<name>' found on PR boundary clock net '<name>'. Static clock nets are not allowed to drive loads inside of a reconfigurable region of type BUFGCE, BUFG_GT or BUFGCTRL. Remove the series buffer inside of the PR region to correct this issue.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 63722 | 2014.4.1 - Vivado UltraScale Partial Reconfiguration - Floorplan limitation for reconfigurable module containing Global Clock Resource | N/A | N/A |
| AR# 63998 | |
|---|---|
| Date | 04/30/2015 |
| Status | Active |
| Type | General Article |
| Tools |
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