AR# 64006

UltraScale/UltraScale+ QDRII+ IP - Unexpected DRC for correct placement of memory clock pair (K/K#)

Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 69038)

Unexpected DRC violations can be displayed for K[1] even when following the MIG Memory Clock (K/K#) allocation rules as follows:

Memory Clock pair must be allocated in one of the byte lanes that are used for the write data of the corresponding memory component.
Memory clock should come from one of the center byte lanes (byte lanes 1 & 2).
K/K# can be allocated to any PN pair.

If the MIG Memory Clock allocation rules are being followed, then this violation is safe to ignore.

Revision History:

04/15/2015 - Initial Release

Was this Answer Record helpful?

Answer Number	Answer Title	Version Found	Version Resolved
69038	UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues	N/A	N/A

AR# 64006
Date	12/15/2017
Status	Active
Type	Known Issues
Devices	Kintex UltraScale Virtex UltraScale Kintex UltraScale+ More Virtex UltraScale+ Zynq UltraScale+ MPSoC Less
Tools	Vivado Design Suite Vivado Design Suite - 2015.1
IP	QDRII+ SRAM

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