AR# 64006

Description

Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 69038)

Unexpected DRC violations can be displayed for K[1] even when following the MIG Memory Clock (K/K#) allocation rules as follows:

• Memory Clock pair must be allocated in one of the byte lanes that are used for the write data of the corresponding memory component.
  
• Memory clock should come from one of the center byte lanes (byte lanes 1 & 2).
  
• K/K# can be allocated to any PN pair.
  

Solution

If the MIG Memory Clock allocation rules are being followed, then this violation is safe to ignore.

Revision History:

04/15/2015 - Initial Release

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