Version Found: DDR4 v7.0
Version Resolved: See (Xilinx Answer 69035)
The MIG UltraScale DDR4/DDR3 memory controller might inadvertently hang (app_rdy stays low indefinitely) when the memory controller Reordering mode is set to "STRICT".
Note: Strict ordering overrides all other controller mechanisms (such as coalesce read requests), and therefore degrades data bandwidth utilization in some workloads.
This is an issue with the memory controller, but there is currently no work-around available.
Please use the "NORM" reordering mode or contact Xilinx Technical Support if the "STRICT" reordering mode is required.
Revision History:
04/15/2015 - Initial Release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 69035 | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues | N/A | N/A |
| 69036 | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues | N/A | N/A |
| AR# 64010 | |
|---|---|
| Date | 01/02/2018 |
| Status | Active |
| Type | Known Issues |
| Devices | |
| Tools | |
| IP | |