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AR# 64019

Vivado Synthesis - ASYNC_REG is not getting applied to registers when applied on net signals in HDL

Description

ASYNC_REG is not getting applied to registers when it is applied on net signals in HDL:

type Reg_Array is array ( CONST_PIPE_STAGES - 1 downto 1 ) of std_logic;
signal sl_arr_RegBank_InOuts : Reg_Array := ( others => '0' );
attribute ASYNC_REG : string;
attribute ASYNC_REG of sl_arr_RegBank_InOuts: signal is "TRUE";
begin

Register_Pipes:
for I in 0 to CONST_PIPE_STAGES - 1 generate 
begin

FFfirst: 
if I = 0 generate 
begin
First_FF : FDRE
generic map (  INIT => '0'  ) 
port map 
(       C => IN_CLK,
CE => '1',
R => '0',
D => IN_DATA, 
Q => sl_arr_RegBank_InOuts( 1 )
);
end generate;

FFmid: 
if I > 0 AND I < CONST_PIPE_STAGES - 1 generate 
begin
Mid_FF : FDRE
generic map (  INIT => '0'  ) 
port map 
( C => IN_CLK,
CE => '1',
R => '0',
D => sl_arr_RegBank_InOuts( I ), 
Q => sl_arr_RegBank_InOuts( I + 1 )
);
end generate;

FFlast: 
if I = CONST_PIPE_STAGES - 1 generate 
begin
Last_FF : FDRE
generic map (  INIT => '0'  ) 
port map 
( C => IN_CLK,
CE => '1',
R => '0',
D => sl_arr_RegBank_InOuts( CONST_PIPE_STAGES - 1 ), 
Q => OUT_DATA
);
end generate;
end generate;

Solution

This is expected behavior.

The ASYNC_REG property can only be applied to cells. 

In the example above it is applied to net signals that are connecting between register instances, and as a result it is ignored.

The attribute can be applied to the cell by using the declarative region between generate and begin as shown below:

if I = CONST_PIPE_STAGES - 1 generate
                                attribute ASYNC_REG of Last_FF :label is "TRUE"; 
                                begin
                                Last_FF : FDRE
                                             generic map 
                                             (
                                                            INIT => '0'  
                                             ) 
                                             port map 
                                             (
                                                            C             => IN_CLK,
                                                            CE           => '1',
                                                            R             => '0',
                                                            D            => sl_arr_RegBank_InOuts( CONST_PIPE_STAGES - 1 ), 
                                                            Q            => OUT_DATA
                                             );                            
end generate; 
AR# 64019
Date 10/19/2018
Status Active
Type Known Issues
Tools
  • Vivado Design Suite
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