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AR# 64031

Vivado Synthesis - Issues using custom attribute in RTL


When using custom attribute in RTL, Vivado Synthesis sometimes attaches the attribute to cells, and other times to nets.

What is the propagation rule for custom attribute?


Custom attributes set in RTL are supported by Vivado Synthesis, but the following should be understood about how it works.

A Custom attribute can be set in the following ways for Verilog and VHDL.


(* my_att = "my_val" *) reg my_signal;


signal my_signal: std_logic;
attribute my_att : string;
attribute my_att of my_signal : signal is "my_val";

When the synthesis tool encounters this type of coding, it will assign that custom attribute to the driver of that signal, and if that driver still exists after synthesis is done, will attach the custom attribute to the driving cell.

However, this will not prevent the driver from being optimized if synthesis thinks it can optimize it.


If you want to ensure that the signal is kept, then you should use the DONT_TOUCH or KEEP attribute on the signal. 

If this is done, then what is kept is the net with the same name as the signal. 

So if a KEEP or DONT_TOUCH attribute is used, the custom attribute will move from the driving cell to the net.

Note: Care should be taken when using the custom attribute.

AR# 64031
Date 04/19/2017
Status Active
Type Known Issues
  • Vivado Design Suite
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