I am getting a CRITICAL WARNING about a cell called FDCPE.
The RTL for this is as follows:
The problem is that while there is a control signal here called "reset" it is not really resetting (to 0) or setting (to 1) the flop.
Instead it is looking for another value that could be 1 or 0.
In order to get this type of logic, the only primitive in the Xilinx arsenal is the FDCPE which has both a set and a reset.
The solution for this is to either make the reset a synchronous reset or change the reset to assign either a 1 or a 0 to the register.
Otherwise, opt_design will fail due to an unresolved black box.
Note: starting from the 2015.3 release, Vivado Synthesis will give this Critical Warning if the design contains either instantiated or inferred FDCPE or FDCP primitives when targeting UltraScale devices.
In versions prior to 2015.3, these primitives are retargeted to a combination of FDCE, FDPE, LDCE and LUT, which could cause potential timing issues.