Xilinx block RAMs support an extra register after the RAM.
To access these, the RTL needs to be written so that the register is after the BRAM.
For example :
However, in the following cases, the output register in the block RAM will not be used and the Slice register will be used instead.
1. If the register was declared with a non-zero initial value:
2. If the register had a non-zero reset value:
If the register has non-zero initial value or reset value, it will not get absorbed into BRAM.
As a work-around, initialize and reset the register with zeros to have the register be absorbed into the BRAM.