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AR# 64055

Using Vivado Simulation Libraries - SIMPRIM Library


When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation.

The Xilinx libraries are divided into categories based on the function of the model.
You must specify different simulation libraries according to the simulation points.

This article describe the SIMPRIM library in more detail.


The SIMPRIM library is used for simulating timing simulation netlists produced after synthesis or implementation.

Note: Timing simulation is supported in Verilog only.

There is no VHDL version of the SIMPRIM library.

Verilog SIMPRIM Library

The Verilog SIMPRIMS library uses the same source as UNISIM with the addition of specify blocks for timing annotation.

The Verilog UNISIM library is located at <Vivado_Install_Dir>/data/verilog/src/unisims.

SIMPRIMS_VER is the logical library name to which the Verilog physical SIMPRIM is mapped.

To specify the Verilog SIMPRIM library, use the correct simulator command-line switch to point to the precompiled libraries, for example:

-L simprims_ver

If you are a VHDL user, you can either run post synthesis and post implementation functional simulation (in which case no standard default format (SDF) annotation is required and the simulation netlist uses the UNISIM library), or run timing simulation by writing out a Verilog simulation netlist from the design.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58895 Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries - UNISIM & SIMPRIM N/A N/A
AR# 64055
Date 03/04/2016
Status Active
Type General Article
  • Vivado Design Suite