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AR# 64069

UltraScale/UltraScale+ Memory IP - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pins


Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 58435)

After prohibits are set on I/O pins within I/O Pin Planner, if the Memory Byte/Bank Planner is opened, the prohibit pins are not honored.

For example, if prohibits are set on I/Os within bank 46 byte 2, the Memory Byte/Bank Planner allows placement of a memory byte group to bank 46 byte 2.

No errors are generated within the Memory Bank/Byte Planner.

However, Tcl errors are generated.


Until this issue is resolved, you will need to do one of the following to work around it:

Manually ensure that memory byte lanes are not assigned to byte lanes containing prohibits.


Move the memory pin(s) assigned to the prohibit location to a free I/O pin within the byte lane after closing the Memory Byte/Bank Planner.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 64069
Date 01/12/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite
  • Vivado Design Suite - 2015.1
  • MIG UltraScale
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