Version Found: MIG UltraScale v7.0
Version Resolved: See (Xilinx Answer 58435)
While Xilinx does not support simulations with memory controllers targeting custom parts, some customers have experienced this behavior and rectified it with the following action.
This is due to the provided *.do simulation scripts located in the ./sim_1/imports/tb/ directory not pointing to the updated location, for example_tb.sv and example_top.sv.
To resolve the issue, run the simulation through Vivado or modify each *.do script to point to the correct location of the files.
example_tb.sv is no longer in ../../../sources_1/imports/mig_0/tb/.
Instead it is in ../../../sources_1/imports/custom_part/custom_part.srcs/sources_1/ip/mig_0/tb/.
Similarly, example_top.sv is no longer in ../../../sources_1/imports/mig_0/rtl/ip_top/.
Instead it is in ../../../sources_1/imports/custom_part/custom_part.srcs/sources_1/ip/mig_0/rtl/ip_top/.
04/15/2015 - Initial Release