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AR# 64131

2014.4 Partial Reconfiguration - phys_opt_design pushes LUT1 inverter across Partial Reconfiguration (PR) boundary from RM to Static logic


My design has a Reconfigurable Module (RM) output that gets inverted just before leaving the RM.
However, in some runs this inverter (LUT1) gets pushed out of the RM and into the Static logic (absorbed into Static LUTs) during phys_opt_design.
For a Flat design, such optimization across the boundary is correct.
However, in PR design, this optimization will introduce a logical function error when importing the other netlist of RP.


The issue is fixed in Vivado 2015.2.
As a work-around in Vivado versions prior to 2015.2, you can add a dont_touch attribute on the PR boundary net.
AR# 64131
Date 04/16/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.4