We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 64134

2015.1 Partial Reconfiguration - DRC HDPR-40 fails to consider if the clock driver is BUFG/BUFH or BUFR


During place_design, an error message is issued that reconfigurable cell 'XX' contains more than 12 input ports driven by clock nets:

ERROR: [Drc 23-20] Rule violation (HDPR-40) Clock Net Rule Violation - Reconfigurable cell 'XX' has '13' input ports driven by clock nets.
This exceeds the allowable 12 clocks per region for 7-series devices.
Resolution: Modify the module interface so the number of input ports driven by clock nets does not exceed the maximum allowable clocks (12) per region.

There are 13 clocks in the reconfigurable cell, however, 5 of them are BUFR, and these clocks resources can be placed properly in the reconfigurable cell.
The DRC needs to be updated to allow more than 12 clocks if some are BUFR resources.


This issue is fixed in Vivado 2015.3.
To work around this issue, you can degrade this DRC error to a warning:

set_property SEVERITY {Warning} [get_drc_checks HDPR-40]

AR# 64134
Date 04/30/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2015.1