We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64157

2015.1 UltraScale Partial Reconfiguration - COR0[23] bit is not set in Partial Reconfiguration "clearing" bit file for all devices


In Vivado 2015.1, COR0[23] is added to flag that the bit file is a partial reconfiguration clearing bit file so that the LabTools can process the file differently.

This bit should be set for all devices, but currently it is only set in SSI devices, not set in monolithic devices.


This issue is fixed in Vivado 2015.2.
AR# 64157
Date 04/30/2015
Status Archive
Type General Article
  • Vivado Design Suite - 2015.1
Page Bookmarked