We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
My post-route partial reconfiguration design has no routing error.
However, after running update_design -black_box on the PR cell, there are now routing errors.
report_route_status reports the following nets as having routing errors:
GLOBAL_LOGIC0 Unrouted Pins -- only the first 10 are listed, use -show_all to get the full list: compressor_a/chunk_ram_0/BU5/RSTRAMARSTRAM compressor_a/chunk_ram_0/BU5/RSTRAMB compressor_a/chunk_ram_0/BU5/RSTREGARSTREG compressor_a/chunk_ram_0/BU5/RSTREGB compressor_a/chunk_ram_1/BU5/RSTRAMARSTRAM compressor_a/chunk_ram_1/BU5/RSTRAMB compressor_a/chunk_ram_1/BU5/RSTREGARSTREG compressor_a/chunk_ram_1/BU5/RSTREGB compressor_a/chunk_ram_2/BU5/RSTRAMARSTRAM compressor_a/chunk_ram_2/BU5/RSTRAMB
write_bitstream also issues the error below:
ERROR: [DRC 23-20] Rule violation (RTSTAT-8) Unrouted 85physical-only net - 1 physical-only net(s) are unrouted. The problem bus(es) and/or net(s) are GLOBAL_LOGIC1.
The "GLOBAL_LOGIC" nets are routed properly, but their routing status is incorrectly reported.