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AR# 64158

2015.1 UltraScale Partial Reconfiguration - "update_design -black_box" causes unrouted net "GLOBAL_LOGIC" (VCC/GND)

Description

My post-route partial reconfiguration design has no routing error.
 
However, after running update_design -black_box on the PR cell, there are now routing errors.
 
report_route_status reports the following nets as having routing errors:
 

GLOBAL_LOGIC0
Unrouted Pins -- only the first 10 are listed, use -show_all to get the full list:
compressor_a/chunk_ram_0/BU5/RSTRAMARSTRAM
compressor_a/chunk_ram_0/BU5/RSTRAMB
compressor_a/chunk_ram_0/BU5/RSTREGARSTREG
compressor_a/chunk_ram_0/BU5/RSTREGB
compressor_a/chunk_ram_1/BU5/RSTRAMARSTRAM
compressor_a/chunk_ram_1/BU5/RSTRAMB
compressor_a/chunk_ram_1/BU5/RSTREGARSTREG
compressor_a/chunk_ram_1/BU5/RSTREGB
compressor_a/chunk_ram_2/BU5/RSTRAMARSTRAM
compressor_a/chunk_ram_2/BU5/RSTRAMB
 

write_bitstream also issues the error below:
 

ERROR: [DRC 23-20] Rule violation (RTSTAT-8) Unrouted 85physical-only net - 1 physical-only net(s) are unrouted. The problem bus(es) and/or net(s) are GLOBAL_LOGIC1.

Solution

The "GLOBAL_LOGIC" nets are routed properly, but their routing status is incorrectly reported.

This issue is fixed in Vivado 2015.2.

AR# 64158
Date Created 04/03/2015
Last Updated 04/30/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
Tools
  • Vivado Design Suite - 2015.1