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AR# 64160

ISE Constraints - How do I calculate the offset value in OFFSET IN Before constraint when the corresponding period constraint of the input clock is defined with reference to another time spec plus a phase difference?


I have two primary clock inputs in my design whose period constraints are defined as follows:

# Both clka and clkb are clocks on the FPGA pads. They are two clocks that are locked by external PLL on board.
#clkb's frequency is a half of clka and is ahead of clka by 11ns
NET "clka" TNM_NET = "clka";
TIMESPEC TS_clka = PERIOD "clka" 24.576 MHz INPUT_JITTER 50 ps;

NET "clkb" TNM_NET = "clkb";
TIMESPEC TS_clkb = PERIOD "clkb" TS_clka / 2 PHASE -11 ns INPUT_JITTER 2 ns;

# the offset in is associated to clkb, 15ns is the time difference between the start of data valid window and the capturing rising clock edge of clkb
NET "data"        OFFSET = IN  15 ns VALID 30 ns BEFORE "clkb" RISING;

However, in the OFFSET IN analysis, the -11 ns phase difference is accounted into clock arrival which is then counted into the slack calculation.
This does not make sense as the  -11 ns is the phase relationship between the two clocks, but not relative to the data and the clock edge.

Is there anything wrong in the timing analysis?


This is expected behavior from the timing analysis based on the OFFSET IN constraint.

The offset value in the OFFSET IN constraint is not relative to the time that the capturing edge arrives at the FPGA pad, but relative to the time 0.
At time 0, the clkb capturing edge is at time -11ns, and the start of data valid is at time -(11+15) = -26ns, so the offset value should be 26.

NET "data"        OFFSET = IN  26 ns VALID 30 ns BEFORE "clkb" RISING;

In this case the Offset In analysis makes sense.

AR# 64160
Date 05/19/2015
Status Active
Type General Article
  • ISE Design Suite