We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64180

MIG - DRC received in write_bitstream for some configurations of the MIG core


Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)


When generating a bitstream for my design, I receive the following DRCs related to the MIG core.

Can they be safely ignored?

[Drc 23-20] Rule violation (REQP-1709) Clock output buffering - PLLE2_ADV connectivity violation. The signal u_mig_7series_test/u_mig_7series_test_mig/u_ddr3_infrastructure/pll_clk3_out on the u_mig_7series_test/u_mig_7series_test_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of u_mig_7series_test/u_mig_7series_test_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
[Drc 23-20] Rule violation (RTSTAT-10) No routable loads - 1 net(s) have no routable loads. The problem net(s) are u_mig_7series_test/u_mig_7series_test_mig/u_iodelay_ctrl/n_0_rst_ref_sync_r_reg[0][14].


These DRCs can occur in some configurations of the MIG core and are safe to ignore.

  1. (REQP-1709)
    This refers to the CLKOUT outputs from the PLL in the MIG core not driving through the same kind of buffer load.
    This is a valid DRC as the CLKOUT signals driving the PHASER_IN/OUT_PHY cells are connected directly from the PLL to the PHASERs and cannot be driven through any buffer type.
    Provided this is the case then this DRC is safe to ignore.
  2. (RTSTAT-10)
    In DDR3 for frequencies > 667 MHz, IODELAY clock can be either 300 or 400 MHz (depending on the FPGA speed grade), otherwise the IODELAY clock is 200 MHz
    As a result 2 resets signals are generated in the MIG, one for the 200MHz clock domain and one for the 300/400 MHz clock domain.
    Depending on the design frequency, only one of these reset signals are used and the other is left unconnected and ignored.
    This DRC is related to the ignored reset signal and can be safely ignored.

Revision History
04/29/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 64180
Date 05/20/2015
Status Active
Type Known Issues
  • Kintex-7
  • Virtex-7
  • Artix-7
  • MIG 7 Series