Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)
When generating a bitstream for my design, I receive the following DRCs related to the MIG core.
Can they be safely ignored?
[Drc 23-20] Rule violation (REQP-1709) Clock output buffering - PLLE2_ADV connectivity violation. The signal u_mig_7series_test/u_mig_7series_test_mig/u_ddr3_infrastructure/pll_clk3_out on the u_mig_7series_test/u_mig_7series_test_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of u_mig_7series_test/u_mig_7series_test_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
[Drc 23-20] Rule violation (RTSTAT-10) No routable loads - 1 net(s) have no routable loads. The problem net(s) are u_mig_7series_test/u_mig_7series_test_mig/u_iodelay_ctrl/n_0_rst_ref_sync_r_reg.