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AR# 64184

7 Series FPGAs Transceiver Wizard v3.5 - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the 7 series FPGAs Transceiver Wizard v3.5 released with the Vivado 2015.1 design tool.

Solution

Release notes:


  •  Updated the GTZ CTLE tuning code to enable tuning of individual lanes.
  •  Added separate resets for TX and RX startup FSMs except for GTZ.
     

Known Issues:


Issue: When Reference clock input frequency is greater than maximum allowed fabric clock frequency, pulse width violations are observed.

 
Work-Around:
 
Instead of connect refclk directly to the cpll railing logic, connect refclk/2 clock.

 
Use Case1:

Below are the steps given to do the same when "Shared logic" is in example design.
 
File1 - <component_name>_gt_usrclk_source.v:
 
1)      Add a new output port REFCLK_DIV2.
2)      Take the output from the ODIV2 pin of IBUFDS_GTE2 and assign it to REFCLK_DIV2 as shown below:
 
IBUFDS_GTE2 ibufds_inst
    (
        .O               (gtrefclk_i),
        .ODIV2           (gtrefclk2_i),
        .CEB             (tied_to_ground_i),
        .I               (GTREFCLK_PAD_P_IN),
        .IB              (GTREFCLK_PAD_N_IN)
    );
 
assign REFCLK_DIV2 = gtrefclk2_i;
 
File2 - <component_name>_support.v:
 
1)      Add an extra port to the <component_name>_gt_usrclk_source module instantiated.
         .REFCLK_DIV2(refclk_div2_i)
2)      Add an extra port to the <component_name> module instantiated.
        .REFCLK_DIV2(refclk_div2_i)
 
File3 -  <component_name>.v:
 
1)      Add a new input port: REFCLK_DIV2
2)      Add an extra port to the <component_name>_init module instantiated
        .REFCLK_DIV2(REFCLK_DIV2)
 
File4-  <component_name>_init.v:
 
1)      Add a new input port REFCLk_DIV2
2)      Add an extra port to the <component_name>_multi_gt module instantiated
         .REFCLK_DIV2(REFCLK_DIV2)
 
File5 - <component_name>_multi_gt.v:
 
1)      Add a new input port REFCLk_DIV2
2)      Change the refclk_in the port connection in the <component_name>_cpll_railing module instantiated
         .refclk_in (REFCLK_DIV2)
 
Use Case2:

Below are the steps given to do the same when "Shared logic" is in IP.
 
File1 - <component_name>_gt_usrclk_source.v :
 
1)      Add a new output port: REFCLK_DIV2
2)      Take the output from the ODIV2 pin of IBUFDS_GTE2 and assign it to REFCLK_DIV2 as shown below:
 
IBUFDS_GTE2 ibufds_inst
    (
        .O               (gtrefclk_i),
        .ODIV2           (gtrefclk2_i),
        .CEB             (tied_to_ground_i),
        .I               (GTREFCLK_PAD_P_IN),
        .IB              (GTREFCLK_PAD_N_IN)
    );
 
Assign REFCLK_DIV2 = gtrefclk2_i;
 
File2 - <component_name>_support.v:
1)      Add an extra port to the <component_name>_gt_usrclk_source module instantiated.
                .REFCLK_DIV2(refclk_div2_i)
2)      Add an extra port to the <component_name>_init module instantiated.
        .REFCLK_DIV2(refclk_div2_i)
 
File3 - <component_name>_init.v :
1)      Add a new input port REFCLk_DIV2
2)      Add an extra port to the <component_name>_multi_gt module instantiated.
        .REFCLK_DIV2(REFCLK_DIV2)
 
File4 - <component_name>_multi_gt.v:
1)      Add a new input port REFCLk_DIV2
2)      Change the refclk_in port connection in the <component_name>_cpll_railing module instantiated.
        .refclk_in (REFCLK_DIV2)
 

 
Revision History:

04/08/2015 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54691 7 Series FPGAs Transceivers Wizard - Release Notes and Known Issues for Vivado 2013.1 and newer versions N/A N/A
AR# 64184
Date Created 04/08/2015
Last Updated 04/30/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.1
IP
  • 7 Series FPGAs Transceivers Wizard