Version Found: MIG UltraScale v7.0
Version Resolved: See (Xilinx Answer 58435)

(PG150) states that the sys_rst is an asynchronous input that must be asserted for a minimum of 20 cycles of the controller clock.

Please disregard the 20 clock cycle requirement.

The sys_rst input port is an asynchronous reset which goes through synchronization logic so the 20 cycle requirement is not required and will be removed from (PG150) in a future release. 

The asynchronous sys_rst port drives the PRE input pins to the MIG IP core synchronization logic but there are no set_false_path timing constraints on this path.

In some designs, this can make timing closure difficult so a set_false_path constraint should be applied to the sys_rst.

To ignore the timing paths for the asynchronous sys_rst to the synchronization logic, the following example constraint can be applied:
 

04/08/2015 - Initial Release