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AR# 64198

UltraScale I/O components reset procedure

Description

When resetting the I/O Components in either native or component mode, there is a recommended reset sequence that should be followed to ensure correct operation.

Solution

Component Mode:

When UltraScale component I/O components (IDELAYCTRL, ISERDESE3, IDDRE3, OSERDESE3, ODDRE3, IDELAYE3 and/or ODELAYE3) are used, then as with native components, it is necessary to follow a certain reset release sequence in order to make a design behave correctly.

Apply this reset release sequence after power up:

  1. Release the systems global reset of the used PLLs and MMCMs
  2. For PLLs and MMCMs this means that they start generating clocks.
  3. When the PLL/MMCM reaches the LOCKED (LOCKED pin is high) state and deliver stable clocks at the outputs, start the sequence to release the reset of the used components.
    • CLKOUT0 and CLKOUT1 outputs of the PLL can be used as the clock for the application design including the reset sequencer.
  4. After the PLL/MMCM reaches the locked state, release the reset inputs of all connected I/O components in this sequence:
    • Release reset of the used delay lines (IDELAYE3, ODELAYE3, note: if using a FIXED delay the RST can be tied low)
    • Release the reset of the used ISERDESE3, IDDRE3, OSERDESE3 and/or ODDRE3
    • Finally release the reset of the IDELAYCTRL.
  5. Wait until the RDY pin of the IDELAYCTRL is asserted high before taking the next step.
  6. After a small delay take the application out of reset.


Remark 1:

  • Between each step of the reset sequence insert a delay.
  • Do this as good design practice to ensure that the reset removal timing is respected.

Remark 2:

  • When using the IDELAYs and/or ODELAYs in TIME mode the sequence described above for reset release must be applied.
  • When using the IDELAYs and/or ODELAYs in COUNT mode the use of an IDELAYCTRL is NOT required.

TIP:

  • The in-between reset delay can be generated by using Flip-flops (FF) or a combination of FFs and SRL (Using SRL has the advantage of generating flexible delays).
  • As outlined above, the PLL or MMCM LOCKED pin is used to start the reset release sequence.

Be aware that the LOCKED signal is an asynchronous signal that need to be synchronized to the used clock before applying it into any circuit.

Reset sequence while a design is running:

  1. Pull the reset of all used components (IDELAYCTRL, ISERDESE3, IDDRE3, OSERDESE3, ODDRE3, IDELAYE3 and/or ODELAYE3) high at once.
  2. When releasing the reset, you do not need to wait for the PLL/MMCM LOCKED pins to go high.
    However, the reset release sequence as described above must be followed.

    1. Release the reset of the used delay lines (IDELAYE3, ODELAYE3)
    2. Release the reset of the used ISERDESE3, IDDRE3, OSERDESE3 and/or ODDRE3
    3. Finally release the reset of the IDELAYCTRL.
    4. Wait until the RDY pin of the IDELAYCTRL is asserted high before continuing.


Native Mode:

When using native mode, the High Speed SelectIO Wizard should be used. For known issues, please see (Xilinx Answer 64216)

When UltraScale native I/O components (BITSLICE_CONTROL, RXTX_BITSLICE, RX_BITSLICE and/or TX_BITSLICE) are used, it is necessary to follow a certain reset release sequence in order to make a design behave correctly.

Apply this reset release sequence after power up:

  1. Release the systems global reset for the used PLLs and MMCMs.
  2. The PLLs and MMCMs will start generating clocks (These are not stable until LOCKED).
  3. Keep the CLKOUTPHY output of the PLL delivering the master clock to the BITSLICE_CONTROL components disabled during the rest of the reset sequence.
  4. When the PLL reaches the LOCKED (LOCKED pin is high) state and is now delivering stable clocks at the CLKOUT0 and CLKOUT1 outputs, start the sequence to release the reset of the used components.
    • CLKOUT0 and CLKOUT1 outputs can be used as a clock for the RIU interface and for the application design including the reset sequencer.
  5. After the PLL reaches the locked state, release the reset inputs of all connected BITSLICEs and BITSLICE_CONTROL in this sequence:
    1. Release the reset of the delay lines of the used BITSLICES (RST_DLY, RST_DLY_EXT, RX_RST_DLY, TX_RST_DLY).
    2. Now release the global reset of the used BITSLICEs (RST, RX_RST, TX_RST).
    3. Finally release the global BITSLICE_CONTROL reset (RST).
  6. After this, enable the CLKOUTPHY clock of the PLL by taking CLKOUTPHYEN high.
  7. Wait until the DLY_RDY and VTC_RDY pins of the BITSLICE_CONTROL are asserted high before taking the next step.
  8. After a small delay, take the application out of reset.

Remark 1:

  • Before releasing any reset be sure to pull the EN_VTC pins of all used BITSLICEs and BITSLICE_CONTROL high.
  • Wait until DLY_RDY and VTC_RDY are high before pulling any of the EN_VTC pins low.

Remark 2:

  • Between each step of the reset sequence insert a delay.
  • Do this as good design practice to be sure that the reset removal timing is respected.

Tip:

  • The in-between reset delay can be generated by using FFs or a combination of FFs and SRL (Using SRL has the advantage of generating flexible delays).
  • As outlined above, the PLL or MMCM LOCKED pin is used to start the reset release sequence.
    Be aware that the LOCKED signal is an asynchronous signal that need to be synchronized to the used clock before applying it into any circuit.

Reset sequence while a design is running:

  • Pull the reset of all used components (BITSLICE_CONTROL, RXTX_BITSLICE, RX_BITSLICE and/or TX_BITSLICE) high at once and disable the CLKOUTPHY clock of the PLL by pulling CLKOUTPHYEN low.
  • When releasing the reset you do not need to wait for the PLL/MMCM LOCKED pins to go high.
    However, the reset release sequence as described above must be followed.
    1. Release reset of the delay lines of the used BITSLICES (RST_DLY, RST_DLY_EXT, RX_RST_DLY, TX_RST_DLY).
    2. Now release the global reset of the used BITSLICEs (RST, RX_RST, TX_RST).
    3. Finally, release the global BITSLICE_CONTROL reset (RST).
    4. After this, enable the CLKOUTPHY clock of the PLL by taking CLKOUTPHYEN high.
    5. Wait until the DLY_RDY and VTC_RDY pins of the BITSLICE_CONTROL are asserted high before continuing.

(UG571) Native Mode Reset Sequence contains an example of how to implement the reset sequence.

An improvement to the Delta circuit is detailed below.

This should be used if the Reset will be used while the design is running and the reset is asserted for > than 32 clock cycles.

This Delta circuit will correctly sequence the resets at startup and any subsequent resets.


 

  • Enable - Input can be used by logic in the FPGA to hold off the reset going low.
  • DlyIn - Connect to the locked output of the PLL (PLL.LOCKED is an asynchronous signal, using a 2 or 3 FF synchronizer is recommended).
  • ClkIn - One of the output clocks of the PLL. Normally the application logic clock is used.
  • Rst - Can be the system reset or can be a reset generated by the application in the FPGA.
  • RSTOUT - Output the reset inputs of BITSLICE, BITSLICE_CONTROL and the application. As an inverted signal, used as connection to the next stages Locked input.
  • C_AppsRstDly - Number of delayed clock cycles.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66012 UltraScale - Known issues list when using component mode for I/O interfaces i.e IODELAY / IOSERDES. N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
64217 High Speed SelectIO Wizard - Reset not following recommended sequence N/A N/A
AR# 64198
Date Created 04/09/2015
Last Updated 08/11/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale