A bank in UltraScale has 52 IOBs.
These are broken down into 4 Bytes that contain 2 nibbles, an upper nibble containing 7 Bitslices and a lower nibble containing 6 Bitslices.
Therefore, you can use 3 differential pairs per nibble, 6 per Byte, 24 differential pairs per bank.
The Wizard allows users to select 23 differential pairs for data and one for the clock input.
If using a single ended IOSTANDARD you can use 7 IOBs in an upper nibble and 6 IOBs in the lower nibble, resulting in 52 available IOBs in a bank.
Currently the Wizard only allows users to select 12 IOBs per Byte.
The Upper Nibble 7th bit is not selectable for each of the Bytes.
To work around this issue you can use the High Speed SelectIO to set up everything else that is required for your interface and generate the output products.
Then replace the .xci file with the <<component name>>.v file and other required files.
The LOC and IOSTANDARD constraints will also need to be added.
They can be found in the <<component name>>.xdc file.
Note: the port names might need to be changed.
Once the files have been replaced you can hand code to add in the 7th Bitslice location in each of the Bytes.
Please refer to (Xilinx Answer 64216) High Speed SelectIO - Known Issue List for the software version that the issue is resolved in.