Currently in the High Speed SelectIO Wizard, an external clock coming in on the GC/QBC pins is used as the system clock for bi-directional interfaces.
This is used as the External Capture clock and it also drives the PLL.
Therefore only the IBUFG_PLL should be used as the CLK Scheme.
Please refer to (Xilinx Answer 64216) High Speed SelectIO - Known Issue List for the software version that the issue is resolved in.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 64216 | High Speed SelectIO Wizard - Known Issue list | N/A | N/A |
| AR# 64236 | |
|---|---|
| Date | 05/14/2015 |
| Status | Active |
| Type | General Article |
| Devices |
|