The first two lines of Table 1-17 in (UG917) are incorrect.
The function / direction and associated pins do not match up with the board schematic (U34), board constraints and Fig 1-21 in (UG917).
It should read:
G25 RX Input LVCMOS18 USB_UART_TX 21 TXD Output
K26 TX Output LVCMOS18 USB_UART_RX 20 RXD Input
The Schematic Net Names USB_UART_TX and USB_UART_RX are named from the perspective of the CP2105GM chip, and are thus opposites from the perspective of the FPGA UART peripheral.
The first two lines of Table 1-17 in (UG917) (v1.1 4-Apr-2015) are incorrect.
Table 1-17 in UG917 v1.2 has been updated as follows:
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