AR# 64258

Zynq-7000 SoC, PS DDRC - When ECC is enabled, CHE_CORR_ECC_ADDR_REG_OFFSET register might report incorrect column address


In Zynq-7000, the ddrc.CHE_CORR_ECC_ADDR_REG_OFFSET and ddrc.CHE_UNCORR_ECC_ADDR_REG_OFFSET registers report row, bank, and address offset of the correctable and uncorrectable data received from DRAM device.

When ECC is enabled, ddrc.CHE_CORR_ECC_ADDR_REG_OFFSET [CORR_ECC_LOG_COL] and ddrc.CHE_UNCORR_ECC_ADDR_REG_OFFSET[UNCORR_ECC_LOG_COL] fields might not update the column address properly depending on the position of the erroneous bit in the received data word. 

For example, the following sequence results into column address not being reported properly by the controller:

AXI Addr -> Expected Reported Address : Actual Reported Address
0x100000 -> row: 0x40, bank:0x0, col 0x0 row : 0x40, bank:0x0, col 0x0
0x100002 -> row: 0x40, bank:0x0, col 0x1 row : 0x40, bank:0x0, col 0x1
0x100004 -> row: 0x40, bank:0x0, col 0x2 row : 0x40, bank:0x0, col 0x0
0x100006 -> row: 0x40, bank:0x0, col 0x3 row : 0x40, bank:0x0, col 0x1
0x100008 -> row: 0x40, bank:0x0, col 0x4 row : 0x40, bank:0x0, col 0x2
0x10000a -> row: 0x40, bank:0x0, col 0x5 row : 0x40, bank:0x0, col 0x3
0x10000c -> row: 0x40, bank:0x0, col 0x6 row : 0x40, bank:0x0, col 0x4
0x10000e -> row: 0x40, bank:0x0, col 0x7 row : 0x40, bank:0x0, col 0x5

Note that in the above scenario, DRAM locations at each of the above addresses has single bit ECC error.


Impact: Minor.
Work-around:None. The column address cannot be recovered, only the row and bank addresses are correct.
Configurations Affected: Systems that use DDR memory and are using ECC.
Device Revision(s) Affected:Refer to (Xilinx Answer 47916) Zynq-7000 Design Advisory Master Answer Record.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 SoC Devices - Silicon Revision Differences N/A N/A
AR# 64258
Date 05/28/2018
Status Active
Type Design Advisory