We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64284

2014.2 Partial Reconfiguration - Clock utilization report does not report the reserved clocks in Partial Reconfiguration (PR) regions


After running report_clock_utilization on a PR design, I get a report on utilized clocks only, without the reserved clocks in the PR region.

In the clock utilization report of a test design, only 7 clocks are reported for X1Y10.

During place_design, I get the following errors complaining about too many clocks used in clock region X1Y10:

ERROR: [Place 30-695] The clock region contains a Reconfigurable Module (RM). Reconfigurable Modules require reservation of clocking resources for all clock regions used by the RM. These clock reservations will affect the number of clock resources available to the rest of the design, and may lead to clocking congestion or over-utilization. Total clock capacity of clock region X1Y10 is 12. There are 13 clocks used: 10 RM clocks reserved, and 3 non-RM clocks. Of the 10 RM reserved clocks, 4 are active in the region.

ERROR: [Place 30-410] Global clock placer placed 13 clocks into clock region X1Y10, and each clock region can only have 12 clocks. An attempt to move the required 1 clocks into other clock regions failed. This could be due to the following reasons: Please add information on reserved clocks in each region for PR designs to enable users to better debug the above error if it occurs.

Can report_clock_utilization be enhanced to include reserved clocks?


In Vivado 2015.1, the reserved clocks in the PR region can be reported even if they have no load in the clock region.
AR# 64284
Date 04/28/2015
Status Archive
Type General Article
  • Vivado Design Suite
Page Bookmarked