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AR# 64289

Vivado Implementation - phys_opt_design inserts several BUFGs in series on a clock net

Description

I have noticed that phys_opt_design has inserted several BUFGs in series on a clock net in a design.

                                |--> Source Sequential cell
 MMCM --> BUFG  |
                                |--> BUFG --> BUFG --> BUFG --> BUFG --> BUFG --> Destination Sequential cell

Why does this happen and what can be done to prevent this?


                               

Solution

This is an expected behavior of phys_opt_design.

it is done to fix timing issues on other paths by inserting BUFGs to balance the clock skew.
 
In general, the overall timing performance will be improved after phys_opt_design when you see this happening.

However, this does indicate that there some issues in the design, for example:
 
1. Bad clock structure that is causing large clock skew.
2. Incorrect or Missing timing exception constraints, which is wasting the effort of phys_opt_design.

To locate these issues, you need to find out what paths are causing phys_opt_design to insert BUFGs.
 
These paths start from or end at the loads of the last inserted BUFG.
 
You can report_timing with "-from" or "-to" on these loads and check if these paths have the issues listed above that cause phys_opt_design to insert BUFGs.
 
If the issue are fixed by an RTL change or by adding Timing exceptions, the BUFG insertion can be avoided.

One example of this kind of issue is when phys_opt_design inserts BUFGs in order to meet timing on a path that is supposed to be a false path.
 
After adding the set_false_path constraint, phys_opt_design does not insert any BUFGs.

Also, a dont_touch property on the clock net will prevent the BUFG insertion.

AR# 64289
Date Created 04/16/2015
Last Updated 05/05/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite