UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 6429: 4.1i NGDBUILD - Virtex timing simulation: DUTY_CYCLE_CORRECTION property on BUFGDLL in UCF file may not be seen by sim model

AR# 6429

4.1i NGDBUILD - Virtex timing simulation: DUTY_CYCLE_CORRECTION property on BUFGDLL in UCF file may not be seen by sim model

Description

Keywords: Virtex, BUFGDLL, CLKDLL, DUTY_CYCLE_CORRECTION, UCF

Urgency: Standard

General Description:
Two of the CLKDLL-related properties can be put on the BUFGDLL element,
and they should control the behavior of the underlying CLKDLL simprim:
these are DUTY_CYCLE_CORRECTION and the new FACTORY_JF.
If these are specified in the UCF file, the new values will not be pushed down
to the underlying CLKDLL, and the simprim won't see them, so the simulation
will not correctly simulate these behaviors.

Solution

To workaround this issue, use the following syntax in the ucf file:

INST <INST name> BUFGDLL/CLKDLL DUTY_CYCLE_CORRECTION=TRUE;
AR# 6429
Date 08/12/2003
Status Archive
Type General Article