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AR# 64299

2017.1 Vivado UltraScale Partial Reconfiguration - Reconfigurable Partition using GTs with CONFIG blocks in same clock Region causes DRC error "HDPR-55"


When I use GTs with CONFIG blocks in the same clock Region for a Reconfigurable Partition (RP), I get the following DRC error:

ERROR: [DRC 23-20] Rule violation (HDPR-55) Reconfigurable Pblock using Global Clock resources must be clock region aligned - HD.RECONFIGURABLE Pblock '<pblock_name>' is not fully aligned on clock region '<clock region name>'.A reconfigurable Pblock that ranges Global Clock sources must use either an entire clock region or none of it. Please re-floorplan to use complete clock regions.

Is this expected behavior?


The above DRC "HDPR-55" is expected in this situation.

This Pblock cannot be floorplaned to use an entire clock region because Vivado does not support CONFIG blocks inside a Reconfigurable Partition.


However, BUFG_GTs with GTs in RP are required to contain the whole clock region.

As a result, there is a limitation that the user must use a clock region that contains a CONFIG site for an RP that contains GTs.

This limitation is described in (UG909) under the heading "Partial Reconfiguration Checklist for UltraScale Device Designs."

AR# 64299
Date 07/06/2017
Status Active
Type General Article
  • Vivado Design Suite