General Description: FPGA Express 3.3 now includes support for the Synopsys compiler directive "dont_touch". This attribute can be set on a module/entity or instantiated cells and will prevent that portion of the design from being changed during synthesis and optimization. The attribute cannot be applied to signals.
NOTE: This attribute only applies to optimization done during synthesis. This attribute is not passed on to the place and route tools.
There are three ways to set the attribute:
Set the dont_touch via the FPGA Express Constraints Editor
Right click on the pre-optimized structure and select Edit Constraints. Under the Modules tab, you will see a column titled "Dont Touch" There are few settings to select from:
TRUE = don't optimize this instance FALSE = optimize this instance (default) INHERIT = this instance takes the setting of the module/entity above it
"all instances" is used when applying an attribute to a module/entity. All instances below that module/entity will receive that particular attribute.
Set the dont_touch attribute directly in the HDL code.
Add this Verilog comment immediately following a module declaration or cell instantiation:
/* synopsys attribute fpga_dont_touch "true" */
Add this VHDL attribute declaration in the architecture before the "begin" keyword:
attribute fpga_dont_touch : string; attribute fpga_dont_touch of <instance> : label is "true";