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AR# 64318: Vivado Partial Reconfiguration - How does Vivado handle a route-through path in a Reconfigurable Partition (RP)
Vivado Partial Reconfiguration - How does Vivado handle a route-through path in a Reconfigurable Partition (RP)
When a connection directly from an input port to an output port (route-through path) is found in a Reconfigurable Partition, how does Vivado handle this path?
1) If the direct path is a non-clock signal:
If it is loadless in both static and dynamic logic, opt_design will insert a LUT1 to split the route-through.
If it has load in static or dynamic logic, no LUT will be inserted in the route-through path
2) If the direct path is a clock signal from static logic:
This is not allowed in a Partial Reconfiguration design and DRC HDPR-41 will be reported:
ERROR: [Drc 23-20] Rule violation (HDPR-41) Clock Net Rule Violation - Reconfigurable cell 'XX' has a route-through (direct connection between input port and output port inside reconfigurable cell) driven by clock net 'clk2_IBUF_BUFG'. This connection is not supported by partial reconfiguration flow. Resolution: Remove the clock net route-through by modifying the module interface.
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