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AR# 64340

Vivado Constraints - Frequently Asked Questions and Common Issues of the create_clock constraint


This Answer Record lists the Frequently Asked Questions and Common Issues encountered with the create_clock constraint.


 Q1. What kind of clocks should be defined with the create_clock constraint?

 A1. The create_clock constraint should only defines these clock types:
  • Primary clocks on input clock ports, or 7 series Gigabit Transceiver (GT) output clock pins.
  • Virtual clocks that do not exist in the design. (See Q2 for more information about virtual clocks)
      Any internal clock except the 7 series GT output clocks should be defined as a generated clock. 
      Vivado supports automatic clock propagation to the UltraScale GT output clock pins, so the UltraScale GT output clocks do not need to be manually constrained. 
      (See Q3 for more information about gigabit transceiver output clocks)
     Further reference:
  • (UG903) Using Constraints - Section "Primary Clocks" and "Virtual Clocks".
  • (Xilinx Answer 59030) - The effect on timing analysis when using create_clock to define a clock on internal objects.
 Q2. What is a Virtual clock?

 A2. A Virtual clock is a clock that does not exist in the design and is usually used to constrain the input and output interface.
       More reference:
  • (UG903) Using Constraints - Section "Virtual Clocks".
  • (Xilinx Answer 59893) - An example where the virtual clock is used to constrain the input delay.
  • (Xilinx Answer 55287) - An example where the virtual clock is used to constrain input to output feed-through paths.

 Q3. How to constrain Gigabit Transceiver (GT) output clocks?

 Q4. How to constrain clocks on differential ports?

 Q5. Critical Warning is reported on a constraint in an IP XDC complaining that a clock object or an object related to clock cannot be found.

       Why does the IP XDC not work?

 A5. The clock from the user design that is used by an IP needs to be defined with create_clock or create_generated_clock in the user XDC and needs to be processed before it is used by the IP constraints.

       These issues are mostly due to missing top level clock definitions or incorrect constraints ordering.
       More reference:
  • (UG903) Using Constraints - Section "Ordering Your Constraints" and "Constraints Scoping".
  • (Xilinx Answer 57056) - An example where the issue occurs due to missing clock definition or incorrect constraints order.
  • (Xilinx Answer 53805) - An example where the issue occurs due to the clock definition being overridden.

AR# 64340
Date 05/19/2015
Status Active
Type General Article
  • Vivado Design Suite
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