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AR# 64351

Vivado Constraints - How to constrain Gigabit Transceiver output clocks?


How do I constrain Gigabit Transceiver (GT) output clocks?


Constraining GT output clocks is supported differently in 7 series and UltraScale devices.

7 series devices:

Although the GT output clocks are internal clocks, they need to be defined with a create_clock constraint on the GT output clock pins for 7 series devices.
This is because there is no timing arc from the GT input clock to output clocks for 7 series devices.

As a result, automatic clock propagation is not supported.

create_clock -name rxoutclk0 -period 3.1024 [get_pins <GT_instance_name>/RXOUTCLK]

UltraScale devices

The timing arcs from the GT input clock to output clocks are added for the UltraScale devices.
Therefore, auto-derived clock constraints will be applied to the GT output clocks by the tool.

You do not need to manually constrain them as long as the GT reference input clock has been constrained.

AR# 64351
Date 05/11/2015
Status Active
Type General Article
  • Vivado Design Suite