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AR# 64366

UltraScale - HR I/O pins might appear to have a weak pull-up enabled between the assertion of PROG_B and when PUDC is sampled on the falling edge of INIT_B.


In UltraScale devices, PUDC dictates the state of the I/Os during configuration.

Regardless of the value of PUDC, if PROG_B is asserted on a configured device, a pull-up may appear on the line HRIO until just after PUDC is sampled on the falling edge of INIT_B.

It is expected that a glitch of 750mV might possibly be seen on a HR pin during a PROG assertion.


For HRIO pins:

If a previously configured device has PROG_B toggled externally or internally, a weak pull-up will appear on HR I/O pins between PROG_B's assertion, and the sample of PUDC on the falling edge of INIT.

Once INIT samples the PUDC pin, PUDC dictates the presence of a weak pull-up during programming.

If a low voltage level needs to be maintained during re-configuration on a HR pin, a pull-down must be present on the pin to ensure that the internal pull-up assertion is kept low enough for the interfacing device.

The weak pull-up strength is documented in the Virtex UltraScale or Kintex UltraScale datasheets, as IRPU.





Note: This pull-up enable behavior does not occur on HP I/O pins.
AR# 64366
Date 05/25/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
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