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AR# 64395: 2014.4 AXI Ethernet: IDELAYS Not Calibrated
2014.4 AXI Ethernet: IDELAYS Not Calibrated
I am using the AXI Ethernet Subsystem IP in my design.
I am trying to adjust the IDELAY value on the rxd and rx_ ctl inputs, but it appears to be working incorrectly.
Debug probes on the reset input and ready output from the IDELAYCTRL component show that the reset is static 1 and the ready is static 0, so I believe the IDELAYs are not being calibrated.
What should I do?
The reason that the reset is driven high is because there is a component called bd_ 0_ eth_ mac_ 0_ support_ resets.vhd that does an OR operation between either an external reset or a NOT of the ready output from the IDELAYCTRL (line 125) to initiate a reset to the IDELAYCTRL.
Because the IDELAYCTRL reset input is high, the ready output stays low and the reset continues to stay high.
Modify the file bd_0_eth_mac_0_support_resets.vhd at line 125 from:
idelayctrl_reset_in <= glbl_rst or not idelayctrl_ready;