AR# 64404: Design Advisory for UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2015.1, 2014.4.1) - Link Training failure due to PHYSTATUS not responding to PHY Operations after Device Configuration
Design Advisory for UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2015.1, 2014.4.1) - Link Training failure due to PHYSTATUS not responding to PHY Operations after Device Configuration
Designs with the UltraScale FPGA Gen3 Integrated Block for PCI Express v4.0 core in Vivado 2015.1, and v3.1(Rev2) in 2014.4.1, fail to train or sometimes downtrain to Gen1 speed intermittently.
This issue occurs due to PHYSTATUS not responding to PHY operations after device configuration.
The behavior is observed after the first PCIe reset after device configuration.
As a result, this issue is seen only on platforms that perform a single reset at boot up and not on platforms that performs at least two PCIe resets upon boot up.
The issue is seen only with Kintex UltraScale Production and Virtex UltraScale ES2 devices in 2015.1 and, Kintex UltraScale Production and Virtex UltraScale VU95 ES2 devices in 2014.4.1, and not with 2014.4.
This is a known issue and has been fixed in Vivado 2015.2.
Please install the patch attached with this answer record, as described below.
This patch is for Vivado 2015.1
Unzip the attached zip file to the directory of your choice.
Open Vivado 2015.1 and create a new project.
Open IP catalog. Right click the core you are using and choose IP Settings.
Click Add Repositories and point it to the location where you have unzipped the patch.
Click OK and you are now ready to generate the core.
If you have previously generated the core, you can choose 'Upgrade IP' on your core.
Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.
After the patch is installed, the version of the core should indicate: v4.0 (Rev. 1).