UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64404

Design Advisory for UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2015.1, 2014.4.1) - Link Training failure due to PHYSTATUS not responding to PHY Operations after Device Configuration

Description

Version Found: v4.0, v3.1(Rev2)

Version Resolved and other Known Issues: See (Xilinx 57945)


Designs with the UltraScale FPGA Gen3 Integrated Block for PCI Express v4.0 core in Vivado 2015.1, and v3.1(Rev2) in 2014.4.1, fail to train or sometimes downtrain to Gen1 speed intermittently.

This issue occurs due to PHYSTATUS not responding to PHY operations after device configuration.

The behavior is observed after the first PCIe reset after device configuration.

As a result, this issue is seen only on platforms that perform a single reset at boot up and not on platforms that performs at least two PCIe resets upon boot up.

The issue is seen only with Kintex UltraScale Production and Virtex UltraScale ES2 devices in 2015.1 and, Kintex UltraScale Production and Virtex UltraScale VU95 ES2 devices in 2014.4.1, and not with 2014.4.


Solution

This is a known issue and has been fixed in Vivado 2015.2.

Please install the patch attached with this answer record, as described below.

  • This patch is for Vivado 2015.1
  • Unzip the attached zip file to the directory of your choice.
  • Open Vivado 2015.1 and create a new project.
  • Open IP catalog. Right click the core you are using and choose IP Settings.
  • Click Add Repositories and point it to the location where you have unzipped the patch.
  • Click OK and you are now ready to generate the core.
  • If you have previously generated the core, you can choose 'Upgrade IP' on your core.
  • Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.

After the patch is installed, the version of the core should indicate: v4.0 (Rev. 1).

Revision History:
07/03/2015 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR64404_Vivado_2015_1_preliminary_rev1.zip 802 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
57945 UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues N/A N/A
AR# 64404
Date Created 04/28/2015
Last Updated 07/03/2015
Status Active
Type Design Advisory
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)