There are known issues for JESD v6.1 in Vivado 2015.1.
These will be resolved in Vivado 2015.2.
- JESD204 Subclass 2 receiver configurations are not correctly aligning SYNC output to internal LMFC:
The JESD204 Rx core is not correctly aligning the SYNC output to its internal LMFC counter.
This causes the system latency not to be deterministic between system restarts when Subclass 2 is used.
Subclass 1 is not affected.
- JESD204 Rx is incorrectly regaining SYNC after loss caused by alignment errors before receiving BCs:
The JESD204B receiver core may, under certain circumstances, not correctly report a loss of sync due to alignment errors.
- This can occur if the alignment of the input stream changes relative to the receiver's internal alignment counter without any other errors occurring.
In most situations, alignment errors are caused by problems in the transmitter that also cause bit errors, and so the receiver correctly loses SYNC and requests resynchronization.
It is possible that a transmitter might alter the output alignment without introducing any other errors or forcing resynchronization by sending repeated BC characters, and expect the receiver to initiate resynchronization.
- A secondary issue also affects alignment error detection when lane 0 is inactive.
The receiver might align the internal alignment counter to lane 0 even if lane 0 is inactive.
This will cause a false alignment error report.
This only affects designs that use the lanes in use register to disable lane 0.
A patch exists for these two Known Issues in Vivado 2015.1.
For more information on the patch required, please see (Xilinx Answer 64524)