ERROR: [Place 30-743] IO/clock placer failed to collectively place all IOs and clock instances. This is likely due to design requirements or user constraints specified in the constraint file such as IO standards, bank/voltage/DCI/VREF specifications, together with the part and package being used for the implementation. Please check the above for any possible conflicts.
ERROR: [Drc 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 15. For example, the following two ports in this bank have conflicting VCCOs:
sys_rst (LVCMOS33, requiring VCCO=3.300) and sys_clk_p (LVDS_25, requiring VCCO=2.500)
ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.