AR# 64450


2015.1 Vivado - How do I debug the error: "ERROR: [Drc 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 15."?


My design fails with the following errors in place_design:

ERROR: [Place 30-743] IO/clock placer failed to collectively place all IOs and clock instances. This is likely due to design requirements or user constraints specified in the constraint file such as IO standards, bank/voltage/DCI/VREF specifications, together with the part and package being used for the implementation. Please check the above for any possible conflicts.

ERROR: [Drc 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 15. For example, the following two ports in this bank have conflicting VCCOs:  

sys_rst (LVCMOS33, requiring VCCO=3.300) and sys_clk_p (LVDS_25, requiring VCCO=2.500)


ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.

How do I debug this issue?


The BIVC-1 error message indicates that there are conflicting IOSTANDARDs in one bank.

These IOSTANDARDs require different VCCOs.

The following debug steps can be used to analyze the indicated conflict:

  1. Open the synthesized design.
  2. Check the ports in the I/O Ports window to examine the IOSTANDARD, Bank assignments, and other relevant attributes.
  3. Check the device SelectIO Resources User Guide (for example, (UG471) for 7 series devices) for details of IOSTANDARD conflicts.

For this design, sys_rst is LVCMOS33, requiring VCCO=3.3v and sys_clk_p is an LVDS_25 input.

As per (UG471), if the LVDS_25 input needs to use VCCO other than 2.5v, its DIFF_TERM property should be false.

By running the command below in the Tcl Console, it is found that the DIFF_TERM of sys_clk_p is 1:

get_property DIFF_TERM [get_ports sys_clk_p]

This issue can be resolved by setting DIFF_TERM property of sys_clk_p to false, as in the following example:

set_property DIFF_TERM false [get_ports sys_clk_p]

AR# 64450
Date 06/09/2015
Status Active
Type General Article
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