Version Found: RLDRAM3 v7.0
Version Resolved: See (Xilinx Answer 69037)
MIG UltraScale RLDRAM3 designs can see tWTR violations at frequencies greater than 750MHz.
At higher frequencies, additional pipeline logic is added to the RLDRAM3 IP, which under certain traffic patterns can cause a tWTR violation during simulation, or data errors in hardware.
This can impact Burst Lengths 2, 4, and 8 but is specific to tWTR (Write then Read to the same address).
If the traffic pattern is known (not random) and will never perform a Write then Read to the same address within the tWTR time, then this issue can be disregarded.
If a work-around is required, please contact Xilinx Technical Support for further assistance.
05/07/2015 - Initial Release