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AR# 64486

MIG UltraScale RLDRAM3 - tWTR violations seen at frequencies greater than 750MHz

Description

Version Found: MIG UltraScale v7.0
Version Resolved: See (Xilinx Answer 58435)

MIG UltraScale RLDRAM3 designs can see tWTR violations at frequencies greater than 750MHz.

At higher frequencies, additional pipeline logic is added to the RLDRAM3 IP, which under certain traffic patterns can cause a tWTR violation during simulation, or data errors in hardware. 

For example:

@         48932281000 tb_top.COMP_INST[0].CIO_MEM.cmd_loop.cmdloop MODEL_ERROR Timing Error                      tWTR_sameaddr check

Solution

This can impact Burst Lengths 2, 4, and 8 but is specific to tWTR (Write then Read to same address).

If the traffic pattern is known (not random) and will never perform a Write then Read to the same address within the tWTR time, then this issue can be disregarded.

If a work-around is required, please contact Xilinx Technical Support for further assistance.

Revision History:
05/07/2015 - Initial Release

Linked Answer Records

Master Answer Records

AR# 64486
Date Created 05/07/2015
Last Updated 05/25/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale