We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64488

UltraScale/UltraScale+ QDRII+ IP - Core generation fails due to invalid Memory Device Interface Speed setting


Version Found: v7.0

Version Resolved: See (Xilinx Answer 69038)


MIG UltraScale QDRII+ IP will fail to generate the IP if the "Memory Device Interface Speed (ps)" is incorrectly set above 450MHz (2222ps) for Burst Length 2 (BL2) designs.

The MIG GUI does not prevent the user from selecting faster speeds for BL2 QDRII+ SRAM memories than are supported which causes core generation to fail with the following messages:

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'C0.QDRIIP BurstLen(C0.QDRIIP_BurstLen)' with value '2' for IP 'SN10_virtexuQDRIIPLUS'. Selected memory type is supported only for a memory device interface speed between 2222 and
INFO: [IP_Flow 19-3438] Customization errors found on 'SN10_virtexuQDRIIPLUS'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.


This only affects MIG UltraScale QDRII+ BL2 designs.

To resolve the issue set the "Memory Device Interface Speed (ps)" to a supported frequency range (450MHz or slower).

Revision History:

05/07/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69038 UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues N/A N/A
AR# 64488
Date 12/15/2017
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite
  • Vivado Design Suite - 2015.1
Page Bookmarked