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AR# 64544

2015.1 UltraScale Partial Reconfiguration - The clock nets from static logic fail to honor the contain/exclude routing

Description

During route_design, I get the following error which shows the clock nets from static logic failing to honor the contain/exclude routing due to a similar node:

ERROR: [Constraints 18-901] HDPostRouteDRC-04: the net gen_cmt[0].u_cmtgen/gen_cmtbuf[0].u_buf/ckout[0] does not honor the contain/exclude routing due to routing nodes: INT_X32Y197/INT_NODE_GLOBAL_14_OUT1
ERROR: [Constraints 18-901] HDPostRouteDRC-04: the net gen_cmt[0].u_cmtgen/gen_cmtbuf[2].u_buf/ckout[0] does not honor the contain/exclude routing due to routing nodes: INT_X32Y188/INT_NODE_GLOBAL_3_OUT1
ERROR: [Constraints 18-901] HDPostRouteDRC-04: the net gen_cmt[0].u_cmtgen/gen_cmtbuf[5].u_buf/ckout[0] does not honor the contain/exclude routing due to routing nodes: INT_X32Y192/INT_NODE_GLOBAL_4_OUT0
ERROR: [Constraints 18-901] HDPostRouteDRC-04: the net gen_cmt[0].u_cmtgen/gen_cmtbuf[8].u_buf/ckout[0] does not honor the contain/exclude routing due to routing nodes: INT_X32Y192/INT_NODE_GLOBAL_15_OUT1
ERROR: [Constraints 18-901] HDPostRouteDRC-04: the net gen_cmt[0].u_cmtgen/gen_cmtbuf[6].u_buf/ckout[0] does not honor the contain/exclude routing due to routing nodes: INT_X32Y182/INT_NODE_GLOBAL_7_OUT1

How can I resolve this issue?

Solution

This issue will be fixed in Vivado 2015.3.

AR# 64544
Date Created 05/13/2015
Last Updated 07/06/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.1