We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64577

2014.3 UltraScale Partial Reconfiguration - Reconfigurable pblock containing GTs is not displayed correctly in Graphical User Interface (GUI)


In a partial reconfiguration design targeting an UltraScale device, I intend to draw a pblock including GTs for the reconfigurable partition.


However, in the device view, the highlighted GT primitives are not included into the reconfigurable pblock.

Is this a display issue only?


This is a display issue only and is fixed in Vivado 2015.3.

In reality, in both the GRID_RANGES and DERIVED_RANGES of the reconfigurable pblock, the whole bank of GTs are selected properly.

AR# 64577
Date 05/28/2015
Status Archive
Type General Article
  • Vivado Design Suite - 2014.3
Page Bookmarked