I am doing a VHDL simulation using the file created from ngd2vhdl (A1.5), and I have Virtex Block Ram in my design. When I try and simulate the BRAM I am seeing 'X' on the output of the read port when I write to the other port, starting at the same address for both ports, but then increment the write port address. Only when the write enable on the write port goes low does the data on the read port go valid.
I am doing the following:
- Same clock for Port A and Port B - Writing to one port (Port A), with WEA high - Reading on the other port (Port B) WEB low - Adress for Port A starts at 0, and increments, loading the memory. - Port B address held static at 0 (same starting address)
The problem you are experiencing is an error in the VHDL simulation model for the RAMB4. The following is the change that will fix the problem. This fix is implemented in the Xilinx 2.1i release. After making the following changes the library will have to be re-compiled.
In every model for [X_]RAMB4_S*_S* in simprim and unisim libraries in Port B code, the following lines should change:
line 11832(In my copy) in 1.5 was
if (VALID_ADDRB AND Tviol_CLKB_CLKA_posedge /= 'X') then DOB_zd := MEM((ADDRESS_B*DIBW + DIBW_1) downto (ADDRESS_B*DIBW)); else DOB_zd := (others => 'X'); end if;
should change to:
if (VALID_ADDRB ) then if ( WEA_ipd = '0' OR Tviol_CLKB_CLKA_posedge /= 'X' OR (HAS_OVERLAP = FALSE)) then DOB_zd := MEM((ADDRESS_B*DIBW + DIBW_1) downto (ADDRESS_B*DIBW)); end if; else DOB_zd := (others => 'X'); end if;
The vhd file will need to be re-compiled for the changes to take effect.