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AR# 64600

LogiCORE IP G.709 FEC Encoder/Decoder v2.1(Rev. 5) - A setup timing violation may occur if Encoder implementation is set to BALANCED or DSP BIAS


If the target device is a Virtex UltraScale speed grade -2 part, and if the IP parameter "Encoder implementation" is set to BALANCED or DSP BIAS, a timing error can occur.

This manifests as a negative slack violation of a setup timing constraint.


The work-around is to set "LUT_BIAS" for the "Encoder implementation" parameter, or to use a Virtex UltraScale speed grade -3 part.

Linked Answer Records

Master Answer Records

AR# 64600
Date 05/28/2015
Status Active
Type General Article
  • Virtex UltraScale
  • Vivado Design Suite - 2015.1
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